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| HM5264165F-75/A60/B60 HM5264805F-75/A60/B60 HM5264405F-75/A60/B60 EO Description Features * * * * * * * * 64M LVTTL interface SDRAM 133 MHz/100 MHz 1-Mword x 16-bit x 4-bank/2-Mword x 8-bit x 4-bank /4-Mword x 4-bit x 4-bank PC/133, PC/100 SDRAM The HM5264165F is a 64-Mbit SDRAM organized as 1048576-word x 16-bit x 4 bank. The HM5264805F is a 64-Mbit SDRAM organized as 2097152-word x 8-bit x 4 bank. The HM5264405F is a 64-Mbit SDRAM organized as 4194304-word x 4-bit x 4 bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II. 3.3 V power supply Clock frequency: 133 MHz/100 MHz (max) LVTTL interface Single pulsed RAS 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8/full page 2 variations of burst sequence Sequential (BL = 1/2/4/8/full page) Interleave (BL = 1/2/4/8) Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. L E0135H10 (Ver. 1.0) (Previous ADE-203-940B (Z)) Apr. 25, 2001 Pr od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 * Programmable CAS latency: 2/3 * Byte control by DQM: DQM (HM5264805F/HM5264405F) DQMU/DQML (HM5264165F) * Refresh cycles: 4096 refresh cycles/64 ms * 2 variations of refresh Auto refresh Self refresh * Full page burst length capability Sequential burst Burst stop capability EO Type No. HM5264165FTT-75* HM5264165FTT-A60 HM5264165FTT-B60 *2 1 Ordering Information HM5264165FLTT-75 *1 HM5264165FLTT-A60 HM5264165FLTT-B60 *2 HM5264805FTT-75 *1 HM5264805FTT-A60 HM5264805FTT-B60 *2 HM5264805FLTT-75 *1 HM5264805FLTT-A60 HM5264805FLTT-B60 *2 HM5264405FTT-75 *1 HM5264405FTT-A60 HM5264405FTT-B60 *2 HM5264405FLTT-75 *1 HM5264405FLTT-A60 HM5264405FLTT-B60 *2 Note: 1. 100 MHz operation at CAS latency = 2. 2. 66 MHz operation at CAS latency = 2. L Frequency 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz CAS latency 3 2/3 3 3 2/3 3 3 2/3 3 3 2/3 3 3 2/3 3 3 2/3 3 Package 400-mil 54-pin plastic TSOP II (TTP-54D) Pr Data Sheet E0135H10 od t uc 2 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264165F) 54-pin TSOP VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC DQML WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS EO Pin Description Pin name A0 to A13 Function Address input Row address Column address DQ0 to DQ15 CS RAS CAS Data-input/output Chip select L Bank select address A12/A13 (BS) CKE VCC VSS VCCQ VSS Q NC Row address strobe command Column address strobe command Pr (Top view) A0 to A11 A0 to A7 Data Sheet E0135H10 3 od Pin name Function WE Write enable CLK Clock input Clock enable DQMU/DQML Input/output mask t uc Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264805F) EO Pin Description Pin name A0 to A13 Function Address input Row address Column address DQ0 to DQ7 CS RAS CAS Data-input/output Chip select 4 54-pin TSOP VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS L Bank select address A12/A13 (BS) CKE VCC VSS VCCQ VSS Q NC Row address strobe command Column address strobe command Pr (Top view) A0 to A11 A0 to A8 Data Sheet E0135H10 od Pin name Function WE Write enable DQM CLK Clock input Clock enable Input/output mask t uc Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264405F) EO Pin Description Pin name A0 to A13 Function Address input Row address Column address DQ0 to DQ3 CS RAS CAS Data-input/output Chip select 54-pin TSOP VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC VCC NC WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS NC VSSQ NC DQ3 VCCQ NC NC VSSQ NC DQ2 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS L Bank select address A12/A13 (BS) CKE VCC VSS VCCQ VSS Q NC Row address strobe command Column address strobe command Pr (Top view) A0 to A11 A0 to A9 Data Sheet E0135H10 5 od Pin name Function WE Write enable DQM CLK Clock input Clock enable No connection Input/output mask Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Block Diagram (HM5264165F) Sense amplifier & I/O bus Sense amplifier & I/O bus Sense amplifier & I/O bus Memory array Memory array Column decoder Memory array Column decoder Sense amplifier & I/O bus Column decoder Column decoder Data Sheet E0135H10 6 DQMU /DQML CLK CKE RAS CAS WE CS EO Column address counter Row decoder Bank 0 4096 row X 256 column X 16 bit A0 to A13 A0 to A7 A0 to A13 Column address buffer Row address buffer Refresh counter Row decoder Row decoder Row decoder L Memory array Bank 1 Bank 2 Bank 3 4096 row X 256 column X 16 bit 4096 row X 256 column X 16 bit 4096 row X 256 column X 16 bit Pr Input buffer Output buffer DQ0 to DQ15 Control logic & timing generator od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Block Diagram (HM5264805F) Sense amplifier & I/O bus Sense amplifier & I/O bus Sense amplifier & I/O bus Memory array Memory array Column decoder Memory array Column decoder Sense amplifier & I/O bus Column decoder Column decoder Data Sheet E0135H10 7 DQM CLK CKE RAS CAS WE CS EO Column address counter Row decoder Bank 0 4096 row X 512 column X 8 bit A0 to A13 A0 to A8 A0 to A13 Column address buffer Row address buffer Refresh counter Row decoder Row decoder Row decoder L Memory array Bank 3 Bank 1 Bank 2 4096 row X 512 column X 8 bit 4096 row X 512 column X 8 bit 4096 row X 512 column X 8 bit Pr Input buffer Output buffer DQ0 to DQ7 Control logic & timing generator od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Block Diagram (HM5264405F) Sense amplifier & I/O bus Sense amplifier & I/O bus Sense amplifier & I/O bus Memory array Memory array Column decoder Memory array Column decoder Sense amplifier & I/O bus Column decoder Column decoder Data Sheet E0135H10 8 DQM CLK CKE RAS CAS WE CS EO Column address counter Row decoder Bank 0 4096 row X 1024 column X 4 bit A0 to A13 A0 to A9 A0 to A13 Column address buffer Row address buffer Refresh counter Row decoder Row decoder Row decoder L Memory array Bank 1 Bank 2 Bank 3 4096 row X 1024 column X 4 bit 4096 row X 1024 column X 4 bit 4096 row X 1024 column X 4 bit Pr Input buffer Output buffer DQ0 to DQ3 Control logic & timing generator od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Functions CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A11 (input pins): Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. Column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) is determined by A0 to A7, A8 or A9 (A7; HM5264165F, A8; HM5264805F, A9; HM5264405F) level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A12/A13 (BS) is precharged. For details refer to the command operation section. A12/A13 (input pins): A12/A13 are bank select signal (BS). The memory array of the HM5264165F, HM5264805F, the HM5264405F is divided into bank 0, bank 1, bank 2 and bank 3. HM5264165F contain 4096-row x 256-column x 16-bit. HM5264805F contain 4096-row x 512-column x 8-bit. HM5264405F contain 4096-row x 1024-column x 4-bit. If A12 is Low and A13 is Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected. CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down mode, clock suspend mode and self refresh mode. DQM, DQMU/DQML (input pins): DQM, DQMU/DQML controls input/output buffers. Read operation: If DQM, DQMU/DQML is High, the output buffer becomes High-Z. If the DQM, DQMU/DQML is Low, the output buffer becomes Low-Z. (The latency of DQM, DQMU/DQML during reading is 2 clocks.) Write operation: If DQM, DQMU/DQML is High, the previous data is held (the new data is not written). If DQM, DQMU/DQML is Low, the data is written. (The latency of DQM, DQMU/DQML during writing is 0 clock.) EO DQ0 to DQ15 (DQ pins): Data is input to and output from these pins (DQ0 to DQ15; HM5264165F, DQ0 to DQ7; HM5264805F, DQ0 to DQ3; HM5264405F). VCC and VCC Q (power supply pins): 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer.) L Pr Data Sheet E0135H10 od t uc 9 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 VSS and V SS Q (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the output buffer.) EO Command Truth Table Command Ignore command No operation Burst stop in full page Precharge select bank Precharge all bank Refresh Mode register set 10 Command Operation The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. CKE Symbol DESL n-1 n H H H H H H x x x x x x x x x x x CS H L L L L L L L L L A0 RAS CAS WE A12/A13 A10 to A11 x H H H H H H L L L L x H H L L L L H H H L x H L H H L L H L L H x x x V V V V V V x x x x x L H L H V L H x V x x x V V V V V x x x V Column address and read command Read with auto-precharge Column address and write command Write with auto-precharge Row address strobe and bank active Note: H: VIH. L: V IL. x: VIH or VIL. V: Valid address input Ignore command [DESL]: When this command is set (CS is High), the SDRAM ignore command input at the clock. However, the internal status is held. No operation [NOP]: This command is not an execution command. However, the internal operations continue. Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page (256; HM5264165F, 512; HM5264805F, 1024; HM5264405F)), and is illegal otherwise. When data input/output is completed for a full page of data, it automatically returns to the start address, and input/output is performed repeatedly. L NOP BST READ READ A WRIT Pr WRIT A ACTV H H PRE H PALL H REF/SELF H MRS V L H L Data Sheet E0135H10 od L L L V t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (BS). After the read operation, the output buffer becomes High-Z. Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal. Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13). Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this command is illegal. Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A12/A13 (BS) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank 0 is activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank 2 is activated. When A12 and A13 are High, bank 3 is activated. Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A12/A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mode register set [MRS]: The SDRAM has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode register configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. EO L Pr Data Sheet E0135H10 od t uc 11 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DQM Truth Table (HM5264165F) CKE Symbol ENBU ENBL MASKU MASKL n-1 H H H H n x x x x DQMU L x H x DQML x L x H EO Command Command 12 Upper byte write enable/output enable Lower byte write enable/output enable Upper byte write inhibit/output disable Lower byte write inhibit/output disable Note: H: VIH. L: V IL. x: VIH or VIL. Write: IDID is needed. Read: I DOD is needed. DQM Truth Table (HM5264805F/HM5264405F) CKE Symbol ENB MASK n-1 H H n x x DQM L H Write enable/output enable Write inhibit/output disable Note: H: VIH. L: V IL. x: VIH or VIL. Write: IDID is needed. Read: I DOD is needed. The SDRAM can mask input/output data by means of DQM, DQMU/DQML. DQMU masks the upper byte and DQML masks the lower byte. (HM5264165F) During reading, the output buffer is set to Low-Z by setting DQM, DQMU/DQML to Low, enabling data output. On the other hand, when DQM, DQMU/DQML is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQM, DQMU/DQML to Low. When DQM, DQMU/DQML is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQMU/DQML. For details, refer to the DQM, DQMU/DQML control section of the SDRAM operating instructions. L Pr Data Sheet E0135H10 od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 CKE Truth Table CKE EO Current state Active Any Clock suspend Idle Idle Idle Self refresh Power down Command n-1 H L L H H H H L L L L n L L H H L L L H H H H CS x x x L L L H L H L H RAS x x x L L H x H x H x CAS x x x L L H x H x H x WE x x x H H H x H x H x Address x x x x x x x x x x x Clock suspend mode entry Clock suspend Clock suspend mode exit Auto-refresh command (REF) Self-refresh entry (SELF) Power down entry Note: H: VIH. L: V IL. x: VIH or VIL. Clock suspend mode entry: The SDRAM enters clock suspend mode from active mode by setting CKE to Low. When command is input during CKE is low, the command is valid. The clock suspend mode changes depending on the current status (1 clock before) as shown below. ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. READ suspend and READ with Auto-precharge suspend: The data being output is held (and continues to be output). WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During clock suspend mode, keep the CKE to Low. Clock suspend mode exit: The SDRAM exits from clock suspend mode by setting CKE to High during the clock suspend state. IDLE: In this state, all banks are not selected, and completed precharge operation. Auto-refresh command [REF]: When this command is input from the IDLE state, the SDRAM starts autorefresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the auto-refresh operation, refresh address and bank select address are generated inside the SDRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 4096 times are required to refresh the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge command is required after auto-refresh. L Power down exit Self refresh exit (SELFX) Pr Data Sheet E0135H10 od t uc 13 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM starts selfrefresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since selfrefresh is performed internally and automatically, external refresh operations are unnecessary. EO Function Truth Table Current state Precharge CS H L L L L L L L L Idle H L L L L L L L L 14 Power down mode entry: When this command is executed during the IDLE state, the SDRAM enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit. Self-refresh exit: When this command is executed during self-refresh mode, the SDRAM can exit from selfrefresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state. Power down exit: When this command is executed at the power down mode, the SDRAM can exit from power down mode. After exiting from power down mode, the SDRAM enters the IDLE state. The following table shows the operations that are performed when each command is issued in each mode of the SDRAM. The following table assumes that CKE is high. RAS x H H H H L L L L x H H H H L L L L L CAS x H H L L H H L L x H H L L H H L L Pr WE Address x x x x DESL H L NOP BST H L H L H L x H L H L H L H L BA, RA x x BA, A10 MODE x x MRS DESL NOP BST BA, RA BA, A10 x MODE MRS Command Operation Enter IDLE after t RP Enter IDLE after t RP NOP ILLEGAL*4 ILLEGAL*4 BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A ACTV BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A ACTV Data Sheet E0135H10 od PRE, PALL NOP*6 REF, SELF NOP NOP NOP PRE, PALL REF, SELF NOP ILLEGAL*4 ILLEGAL ILLEGAL t uc ILLEGAL*5 ILLEGAL*5 Bank and row active Refresh Mode register set HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Current state Row active CS H L L L L L L L L RAS x H H H H L L L L x CAS x H H L L H H L L x WE x H L H L H L H L x H L H L Address x x x Command DESL NOP BST Operation NOP NOP NOP Begin read Begin write Other bank active ILLEGAL on same bank*3 Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop to full page Continue burst read to CAS latency and New read Term burst read/start write Other bank active ILLEGAL on same bank*3 Term burst read and Precharge ILLEGAL ILLEGAL EO Read H L L L L L L L L Read with autoprecharge H L L L L L L L L BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE x x x ACTV PRE, PALL REF, SELF MRS DESL NOP BST L H H H H L L L L x H H H H L L L L H H L L H H L L x H H L L H H L L BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A ACTV PRE, PALL Pr H L BA, RA BA, A10 x H L x H L H L H L H L MODE x MRS DESL NOP BST x x BA, RA BA, A10 x MODE MRS REF, SELF BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A ACTV Data Sheet E0135H10 15 od PRE, PALL REF, SELF Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL*4 ILLEGAL*4 t uc Other bank active ILLEGAL on same bank*3 ILLEGAL*4 ILLEGAL ILLEGAL HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Current state Write CS H L L L L L L L L RAS x H H H H L L L L x CAS x H H L L H H L L x WE x H L H L H L H L x H L Address x x x Command DESL NOP BST Operation Continue burst to end Continue burst to end Burst stop on full page Term burst and New read Term burst and New write Other bank active ILLEGAL on same bank*3 Term burst write and Precharge*2 ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL*4 ILLEGAL*4 Other bank active ILLEGAL on same bank*3 ILLEGAL*4 ILLEGAL EO Write with autoprecharge H L L L L L L L L Refresh (autorefresh) H L L L L L L L L Notes: 1. 2. 3. 4. 5. 6. 16 BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE x x x ACTV PRE, PALL REF, SELF MRS DESL NOP BST H: VIH. L: V IL. x: VIH or VIL. The other combinations are inhibit. An interval of t DPL is required between the final valid data input and the precharge command. If tRRD is not satisfied, this operation is illegal. Illegal for same bank, except for another bank. Illegal for all banks. NOP for same bank, except for another bank. L H H H H L L L L x H H H H L L L L H H L L H H L L x H H L L H H L L Pr H L H L BA, RA BA, A10 x H L x H L H L H L H L MODE x MRS DESL NOP BST x x BA, RA BA, A10 x MODE MRS BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A ACTV PRE, PALL REF, SELF BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A ACTV Data Sheet E0135H10 od PRE, PALL REF, SELF ILLEGAL Enter IDLE after t RC Enter IDLE after t RC Enter IDLE after t RC ILLEGAL*5 ILLEGAL*5 t uc ILLEGAL*5 ILLEGAL*5 ILLEGAL ILLEGAL HM5264165F/HM5264805F/HM5264405F-75/A60/B60 From PRECHARGE state, command operation To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM enters the IDLE state after tRP has elapsed from the completion of precharge. EO From IDLE state, command operation To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The SDRAM enters refresh mode (auto-refresh or self-refresh). To [MRS]: The SDRAM enters the mode register set cycle. From ROW ACTIVE state, command operation To [DESL], [NOP] or [BST]: These commands result in no operation. To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands set the SDRAM to precharge mode. (However, an interval of tRAS is required.) From READ state, command operation To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the SDRAM enters precharge mode. L Pr Data Sheet E0135H10 od t uc 17 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 From READ with AUTO-PRECHARGE state, command operation To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the SDRAM then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. EO 18 From WRITE state, command operation To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the SDRAM then enters precharge mode. From WRITE with AUTO-PRECHARGE state, command operation To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the synchronous DRAM enters precharge mode. To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. From REFRESH state, command operation To [DESL], [NOP], [BST]: After an auto-refresh cycle (after tRC), the SDRAM automatically enters the IDLE state. L Pr Data Sheet E0135H10 od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Simplified State Diagram EO WRITE SUSPEND WRITEA SUSPEND POWER APPLIED SELF REFRESH SR ENTRY SR EXIT MODE REGISTER SET MRS IDLE REFRESH *1 AUTO REFRESH CKE CKE_ IDLE POWER DOWN Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. L BST (on full page) ACTIVE CLOCK SUSPEND ACTIVE CKE_ CKE Automatic transition after completion of command. Transition resulting from command input. Pr ROW ACTIVE WRITE Write CKE_ CKE WRITE WRITE WITH AP READ READ WITH AP WRITE WRITE WITH AP CKE_ WRITEA CKE READ WITH AP WRITE WITH AP PRECHARGE PRECHARGE PRECHARGE POWER ON PRECHARGE PRECHARGE BST (on full page) READ Read CKE_ CKE READ WITH AP READ SUSPEND READ Data Sheet E0135H10 19 od CKE_ CKE READA READA SUSPEND t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Mode Register Configuration The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A13, A12, A11, A10, A9, A8: (OPCODE): The SDRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. Burst read and burst write: Burst write is performed for the specified burst length starting from the column address specified in the write cycle. Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set. A6, A5, A4: (LMODE): These pins specify the CAS latency. A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected. A2, A1, A0: (BL): These pins specify the burst length. EO A13 A12 A11 A13 A12 A11 A10 0 X X X 0 X X X 0 X X X 0 X X X 20 L A10 A9 A8 OPCODE 0 0 0 0 1 0 0 1 1 X 0 1 0 1 X A9 0 0 1 1 A8 0 1 0 1 A6 A5 A4 CAS latency R R 2 3 R Pr A7 0 A6 A5 A4 LMODE 1 Write mode Burst read and burst write R Burst read and single write R A3 BT A2 A1 BL A0 Data Sheet E0135H10 od A3 Burst type 0 Sequential Interleave 0 0 0 0 1 1 1 0 0 1 1 0 1 1 1 0 A2 A1 A0 0 1 0 1 0 1 0 Burst length BT=0 1 2 4 8 R R R BT=1 1 2 4 8 R R R R F.P. = Full Page R is Reserved (inhibit) X: 0 or 1 t uc 1 F.P. HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Burst Sequence Burst length = 2 A0 0 1 Sequential Interleave 0, 1, 1, 0, 0, 1, 1, 0, Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, 0 1 0 1 0 1 0 1 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6, A0 0 1 0 1 Sequential 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, EO Starting Ad. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 Starting Ad. Addressing(decimal) Burst length = 8 A0 Sequential L Pr Data Sheet E0135H10 od t uc 21 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Operation of the SDRAM Read/Write Operations EO CAS Latency CLK Command ACTV Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the status of the A12/A13 pin, and the row address (AX0 to AX11) is activated by the A0 to A11 pins at the bank active command cycle. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CAS Latency - 1) cycle after read command set. HM5264165F, HM5264805F series, HM5264405F can perform a burst read operation. The burst length can be set to 1, 2, 4, 8 or full-page (256; HM5264165F, 512; HM5264805F, 1024; HM5264405F). The start address for a burst read is specified by the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13) at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the CAS Latency. The CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4, 8, the Dout buffer automatically becomes High-Z at the next clock after the successive burst-length data has been output. The CAS latency and burst length must be specified at the mode register. L t RCD READ Row Column Pr out 0 out 1 out 0 out 2 out 1 od out 3 Address t uc out 3 CL = CAS latency Burst Length = 4 Dout CL = 2 CL = 3 out 2 Data Sheet E0135H10 22 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Burst Length EO CLK t RCD Command Address ACTV READ Row Column BL = 1 BL = 2 BL = 4 BL = 8 out 0 out 0 out 1 out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8 out 0-1 Dout BL = full page Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9, A8) of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13) at the write command set cycle. L t RCD ACTV WRIT out 0 out 1 BL : Burst Length CAS Latency = 2 Pr in 1 in 1 in 1 in 1 in 2 in 2 in 2 od t uc in 0-1 CLK Command Address Row Column BL = 1 BL = 2 in 0 in 0 Din in 0 in 3 in 3 in 3 in 4 in 4 in 5 in 5 in 6 in 6 in 7 in 7 BL = 4 in 0 BL = 8 in 0 in 8 in 0 in 1 BL = full page CAS Latency = 2, 3 Data Sheet E0135H10 23 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is only written to the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0 clock). EO CLK Command Address Din t RCD ACTV WRIT Row Column Auto Precharge Read with auto-precharge: In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by l APR is required before execution of the next command. L ACTV lRAS READ A ACTV lRAS READ A in 0 Pr Precharge start cycle 2 cycle before the final data is output 1 cycle before the final data is output out0 CAS latency 3 2 od out1 out2 out3 lAPR out0 out1 out2 Burst Read (Burst Length = 4) CLK CL=2 Command ACTV t uc ACTV out3 lAPR DQ (input) CL=3 Command DQ (input) Note: Internal auto-precharge starts at the timing indicated by " ". And an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ". Data Sheet E0135H10 24 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write with auto-precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval of lAPW is required between the final valid data input and input of next command. Burst Write (Burst Length = 4) EO CLK Command DQ (input) ACTV WRIT A ACTV Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ". L CLK ACTV IRAS in0 in1 in2 in3 lAPW Pr WRIT A Single Write od ACTV Command IRAS DQ (input) in t uc 25 lAPW Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ". Data Sheet E0135H10 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Full-page Burst Stop Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. The timing from command input to the last data changes depending on the CAS latency setting. In addition, the BST command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8. CAS latency 2 3 BST to valid data 1 2 BST to high impedance 2 3 EO CLK Command DQ (output) out CLK Command DQ (output) out CAS Latency = 2, Burst Length = full page CAS Latency = 3, Burst Length = full page L out out Pr out out out out out out BST out l BSH = 2 clocks l BSR = 1 clock Data Sheet E0135H10 26 od BST l BSR = 2 clocks t uc out out l BSH = 3 clocks HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same clock as the BST command, and in subsequent clocks. In addition, the BST command is only valid during full-page burst mode, and is illegal with burst lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge command. Burst Length = full page EO CLK Command DQ (input) BST PRE/PALL L in in t DPL I BSW = 0 clock Pr Data Sheet E0135H10 27 od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Command Intervals Read command to Read command interval: 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (same ROW address in same bank) EO CLK Command Address BS ACTV Row Dout Bank0 Active 2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. 3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (different bank) CLK Command Address ACTV Row 0 BS Dout Bank0 Active Bank3 Bank0 Bank3 Active Read Read L READ READ Column A Column B out A0 out B0 out B1 out B2 out B3 Column =A Column =B Column =A Column =B Dout Read Read Dout ACTV Row 1 Pr READ READ Column A Column B CAS Latency = 3 Burst Length = 4 Bank 0 Data Sheet E0135H10 28 od out A0 out B0 out B1 out B2 out B3 Bank0 Bank3 Dout Dout t uc CAS Latency = 3 Burst Length = 4 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write command to Write command interval: 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes, the second write command has priority. WRITE to WRITE Command Interval (same ROW address in same bank) EO CLK Command Address ACTV Row WRIT WRIT BS Din 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. In the case of burst write, the second write command has priority. WRITE to WRITE Command Interval (different bank) CLK Command Address BS ACTV ACTV WRIT WRIT Din Bank0 Active L Column A Column B in A0 in B0 in B1 in B2 in B3 Bank0 Active Column =A Column =B Write Write Burst Write Mode Burst Length = 4 Bank 0 Pr Row 1 Column A Column B od in B2 in B3 t uc Burst Write Mode Burst Length = 4 Row 0 in A0 in B0 in B1 Bank3 Bank0 Bank3 Active Write Write Data Sheet E0135H10 29 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read command to Write command interval: 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. READ to WRITE Command Interval (1) EO CLK Command DQM, CL=2 DQMU /DQML READ WRIT Din Dout READ to WRITE Command Interval (2) DQM, DQMU/DQML CL=2 2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command. 3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. L CL=3 in B0 High-Z in B1 in B2 in B3 Burst Length = 4 Burst write Pr READ CLK Command WRIT od 2 clock High-Z Dout CL=3 High-Z Din t uc Data Sheet E0135H10 30 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write command to Read command interval: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. WRITE to READ Command Interval (1) EO CLK Command DQM, DQMU/DQML Din Dout CLK Command DQM, DQMU/DQML Din Dout WRIT READ WRITE to READ Command Interval (2) 2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command. 3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address). L in A0 out B0 Column = A Write Column = B Read out B1 out B2 out B3 Burst Write Mode CAS Latency = 2 Burst Length = 4 Bank 0 WRIT in A0 Column = A Write Pr READ in A1 Column = B Read CAS Latency Column = B Dout Data Sheet E0135H10 31 od out B0 out B1 out B2 CAS Latency Column = B Dout out B3 Burst Write Mode CAS Latency = 2 Burst Length = 4 Bank 0 t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid. The internal auto-precharge of one bank starts at the next clock of the second command. Read with Auto Precharge to Read Command Interval (Different bank) EO CLK Command BS Dout CLK Command BS Din READ A READ Note: Internal auto-precharge starts at the timing indicated by " 2. Same bank: The consecutive read command (the same bank) is illegal. Write with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts at the next clock of the second command . Write with Auto Precharge to Write Command Interval (Different bank) Note: Internal auto-precharge starts at the timing indicated by " 2. Same bank: The consecutive write command (the same bank) is illegal. L bank0 Read A WRIT A in A0 bank0 Write A in A1 out A0 bank3 Read out A1 out B0 out B1 CAS Latency = 3 Burst Length = 4 ". Pr WRIT in B0 bank3 Write in B1 Data Sheet E0135H10 32 od in B2 in B3 ". t uc Burst Length = 4 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. The internal auto-precharge of one bank starts at the next clock of the second command. Read with Auto Precharge to Write Command Interval (Different bank) EO DQM, DQMU/DQML CLK READ A WRIT Command BS 2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command. L CL = 2 CL = 3 Din Dout bank0 Read A in B0 in B1 in B2 in B3 High-Z Note: Internal auto-precharge starts at the timing indicated by " Pr bank3 Write Burst Length = 4 ". Data Sheet E0135H10 33 od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. However, in case of a burst write, data will continue to be written until one clock before the read command is executed. The internal auto-precharge of one bank starts at the next clock of the second command. Write with Auto Precharge to Read Command Interval (Different bank) EO CLK Command BS DQM, DQMU/DQML Din Dout 34 WRIT A READ Note: Internal auto-precharge starts at the timing indicated by " Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. . It is necessary to separate the two commands with a bank active command. L in A0 out B0 out B1 out B2 out B3 CAS Latency = 3 Burst Length = 4 ". Pr bank3 Read bank0 Write A Data Sheet E0135H10 od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the clocks defined by lHZP , there is a case of interruption toburst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (same bank): To output all data CAS Latency = 2, Burst Length = 4 EO CLK Command Dout CLK Command Dout CAS Latency = 3, Burst Length = 4 L READ out A0 out A1 CL=2 READ out A0 CL=3 PRE/PALL out A2 out A3 Pr PRE/PALL l EP = -1 cycle Data Sheet E0135H10 35 od out A1 out A2 out A3 l EP = -2 cycle t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 READ to PRECHARGE Command Interval (same bank): To stop output data CAS Latency = 2, Burst Length = 1, 2, 4, 8, full page burst EO CLK Command Dout READ PRE/PALL High-Z out A0 l HZP =2 CAS Latency = 3, Burst Length = 1, 2, 4, 8, full page burst L READ PRE/PALL CLK Command Pr High-Z out A0 l HZP =3 Dout Data Sheet E0135H10 36 od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of DQM, DQMU/DQML for assurance of the clock defined by t DPL. EO CLK Command DQM, DQMU/DQML Din WRITE to PRECHARGE Command Interval (same bank) Burst Length = 4 (To stop write operation) WRIT PRE/PALL L tDPL Pr PRE/PALL CLK Command DQM, DQMU/DQML Din WRIT in A0 in A1 od PRE/PALL tDPL Burst Length = 4 (To write all data) CLK Command DQM, DQMU/DQML WRIT t uc 37 Din in A0 in A1 in A2 in A3 tDPL Data Sheet E0135H10 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Bank active command interval: 1. Same bank: The interval between the two bank-active commands must be no less than tRC. EO CLK Command ACTV Address ROW BS Bank 0 Active 2. In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. Bank Active to Bank Active for Same Bank ACTV Bank Active to Bank Active for Different Bank CLK Command Address L t RC ROW Bank 0 Active ACTV ROW:0 Pr ACTV ROW:1 t RRD Bank 3 Active od t uc BS Bank 0 Active Data Sheet E0135H10 38 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than lRSA . EO CLK Command Address MRS ACTV CODE BS & ROW L I RSA Bank Active Mode Register Set Pr Data Sheet E0135H10 39 od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DQM Control The DQM mask the DQ data. The DQMU and DQML mask the upper and lower bytes of the DQ data, respectively. The timing of DQMU/DQML is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQM, DQMU/DQML. By setting DQM, DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM, DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQM, DQMU/DQML during reading is 2 clocks. Writing: Input data can be masked by DQM, DQMU/DQML. By setting DQM, DQMU/DQML to Low, data can be written. In addition, when DQM, DQMU/DQML is set to High, the corresponding data is not written, and the previous data is held. The latency of DQM, DQMU/DQML during writing is 0 clock. Reading DQM, DQMU/DQML DQ (input) 40 ; ;; in 0 in 1 in 3 l DID = 0 Latency EO CLK DQM, DQMU/DQML DQ (output) L CLK Pr out 0 out 1 lDOD = 2 Latency High-Z out 3 od t uc Writing Data Sheet E0135H10 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Refresh Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the autorefresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4096 cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer becomes HighZ after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A selfrefresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below. (1) Enter self-refresh mode within 15.6 s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. (2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 s after exiting from self-refresh mode. EO Others Power-down mode: The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed. Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details, refer to the "CKE Truth Table". Power-up sequence: The SDRAM should be gone on the following sequence with power up. The CLK, CKE, CS, DQM, DQMU/DQML and DQ pins keep low till power stabilizes. The CLK pin is stabilized within 100 s after power stabilizes before the following initialization sequence. The CKE and DQM, DQMU/DQML is driven to high between power stabilizes and the initialization sequence. This SDRAM has VCC clamp diodes for CLK, CKE, CS, DQM, DQMU/DQML and DQ pins. If these pins go high before power up, the large current flows from these pins to VCC through the diodes. Initialization sequence: When 200 s or more has past after the above power-up sequence, all banks must be precharged using the precharge command (PALL). After t RP delay, set 8 or more auto refresh commands (REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by keeping DQM, DQMU/DQML and CKE to High, the output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed with a number of device. L Pr Data Sheet E0135H10 od t uc 41 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Power up sequence 100 s Initialization sequence 200 s EO VCC, VCCQ CKE, DQM, DQMU/DQML CLK CS, DQ Parameter Power dissipation Operating temperature Storage temperature Note: Parameter Supply voltage Input high voltage Input low voltage Notes: 1. 2. 3. 4. 5. 42 0V Low Low Low Power stabilize Absolute Maximum Ratings Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current 1. Respect to V SS . DC Operating Conditions (Ta = 0 to +70C) Symbol VCC, VCCQ VSS , VSS Q VIH VIL All voltage referred to VSS . The supply voltage with all VCC and V CCQ pins must be on the same level. The supply voltage with all VSS and VSS Q pins must be on the same level. VIH (max) = VCC + 2.0 V for pulse width 3 ns at VCC. VIL (min) = VSS - 2.0 V for pulse width 3 ns at VSS . L Symbol VT Value -0.5 to VCC + 0.5 ( 4.6 (max)) -0.5 to +4.6 50 Unit V V mA W C C Note 1 1 Pr VCC Iout PT 1.0 Topr Tstg Min 3.0 0 2.0 -0.3 0 to +70 -55 to +125 Data Sheet E0135H10 od Max 3.6 0 VCC + 0.3 0.8 Unit Notes 1, 2 3 V V t uc V 1, 4 V 1, 5 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 VIL/VIH Clamp This SDRAM has VIL and V IH clamp for CLK, CKE, CS, DQM and D/Q pins. Minimum VIL Clamp Current I (mA) -32 -25 -19 -13 -8 -4 -2 -0.6 0 I (mA) EO VIL (V) -2 -1.8 -1.6 -1.4 -1.2 -1 -0.9 -0.8 -0.6 -0.4 -0.2 0 -10 -15 -20 -25 -30 -35 L 0 -2 -5 -1.5 Pr 0 0 0 Data Sheet E0135H10 43 od -1 -0.5 VIL (V) 0 t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Minimum VIH Clamp Current VIH (V) I (mA) 10 8 5.5 3.5 1.5 0.3 0 0 0 0 0 I (mA) EO VCC + 2 VCC + 1.8 VCC + 1.6 VCC + 1.4 VCC + 1.2 VCC + 1 VCC + 0.8 VCC + 0.6 VCC + 0.4 VCC + 0.2 VCC + 0 L 10 8 6 4 2 0 VCC + 0 VCC + 0.5 Pr VCC + 1 Data Sheet E0135H10 44 od VCC + 1.5 VIH (V) VCC + 2 t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 IOL/IOH Characteristics IOL (mA) EO Vout (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 250 200 150 100 50 0 0 Output Low Current (IOL) I OL Min (mA) 0 27 41 51 58 I OL Max (mA) 0 71 108 134 151 188 194 203 209 212 220 223 L 70 72 75 77 77 Pr 80 81 0.5 1 1.5 2 Vout (V) 2.5 Data Sheet E0135H10 45 od 3 3.5 min max t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Output High Current (I OH ) (Ta = 0 to +70C, VCC, VCCQ = 3.0 V to 3.45 V, VSS, VSSQ = 0 V) I OH I OH Max (mA) -3 -28 -75 -130 -154 -197 -227 -248 -270 -285 -345 -503 IOH (mA) EO Vout (V) 3.45 3.3 3 2.6 2.4 2 1.8 1.65 1.5 1.4 1 0 0 0 0.5 -100 -200 -300 -400 -500 -600 46 Min (mA) -- -- 0 -21 -34 -59 -67 -73 -78 -81 -89 -93 L 1 Pr 1.5 2 2.5 Vout (V) 3 3.5 Data Sheet E0135H10 od min max t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DC Characteristics (Ta = 0 to +70C, VCC, VCC Q = 3.3 V 0.3 V, VS S, V SSQ = 0 V) (HM5264165F) EO Parameter Operating current (CAS latency = 2) (CAS latency = 3) Burst operating current (CAS latency = 2) (CAS latency = 3) Refresh current Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage HM5264165F -75 Symbol Min I CC1 I CC1 -- -- -- -- -- -- -- -- -- -- -A60 -B60 Notes 1, 2, 3 Max Min Max Min Max Unit Test conditions 65 65 1.5 1 10 5 4 3 -- -- -- -- -- -- -- -- -- -- 65 65 1.5 1 10 5 4 3 -- -- -- -- -- -- -- -- -- -- 65 65 1.5 1 10 5 4 3 18 12 mA mA mA mA mA mA mA mA mA mA CKE = VIL, t CK = 12 ns CKE = VIL, t CK = CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK = CKE = VIL, t CK = 12 ns CKE = VIL, t CK = CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK = Burst length = 1 t RC = min Standby current in power down I CC2P Standby current in power down I CC2PS (input signal stable) Standby current in non power down Standby current in non power down (input signal stable) I CC2N 6 7 4 9 1, 2, 6 2, 7 1, 2, 4 2, 9 Active standby current in power I CC3P down Active standby current in power I CC3PS down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable) I CC3N Self refresh current (L-version) I CC6 I LI I LO VOH VOL L I CC2NS I CC3NS I CC4 I CC4 I CC5 I CC6 Pr 18 12 18 12 -- -- -- -- -- -1 65 80 -- -- 65 65 -- -- 110 -- 1 0.4 1 -- -- -1 110 -- 1 -- -- -1 0.4 1 -1.5 1.5 2.4 -- -- 0.4 -1.5 1.5 2.4 -- -- 0.4 2.4 -- Data Sheet E0135H10 47 od 65 65 mA mA 110 mA 1 mA 0.4 1 mA A A V V -1.5 1.5 -- 0.4 t CK = min, BL = 4 1, 2, 5 t RC = min 3 8 VIH VCC - 0.2 V VIL 0.2 V 0 Vin VCC t uc 0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DC Characteristics (Ta = 0 to +70C, VCC, VCC Q = 3.3 V 0.3 V, VS S, V SSQ = 0 V) (HM5264805F) EO Parameter Operating current (CAS latency = 2) (CAS latency = 3) Burst operating current (CAS latency = 2) (CAS latency = 3) Refresh current Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage 48 HM5264805F -75 Symbol Min I CC1 I CC1 -- -- -- -- -- -- -- -- -- -- -A60 -B60 Notes 1, 2, 3 Max Min Max Min Max Unit Test conditions 60 60 1.5 1 10 5 4 3 -- -- -- -- -- -- -- -- -- -- 60 60 1.5 1 10 5 4 3 -- -- -- -- -- -- -- -- -- -- 60 60 1.5 1 10 5 4 3 18 12 mA mA mA mA mA mA mA mA mA mA CKE = VIL, tCK = 12 ns CKE = VIL, t CK = CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK = CKE = VIL, tCK = 12 ns CKE = VIL, t CK = CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK = Burst length = 1 t RC = min Standby current in power down I CC2P Standby current in power down I CC2PS (input signal stable) Standby current in non power down Standby current in non power down (input signal stable) I CC2N 6 7 4 9 1, 2, 6 2, 7 1, 2, 4 2, 9 Active standby current in power I CC3P down Active standby current in power I CC3PS down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable) I CC3N Self refresh current (L-version) I CC6 I LI I LO VOH VOL L I CC2NS I CC3NS I CC4 I CC4 I CC5 I CC6 Pr 18 12 18 12 -- -- -- -- -- -1 60 75 -- -- 60 60 -- -- 110 -- 1 0.4 1 -- -- -1 110 -- 1 -- -- -1 0.4 1 -1.5 1.5 2.4 -- -- 0.4 -1.5 1.5 2.4 -- -- 0.4 2.4 -- Data Sheet E0135H10 od 60 60 mA mA 110 mA 1 mA 0.4 1 mA A A V V -1.5 1.5 -- 0.4 t CK = min, BL = 4 1, 2, 5 t RC = min 3 8 VIH VCC - 0.2 V VIL 0.2 V 0 Vin VCC t uc 0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DC Characteristics (Ta = 0 to +70C, VCC, VCC Q = 3.3 V 0.3 V, VS S, V SSQ = 0 V) (HM5264405F) EO Parameter Operating current (CAS latency = 2) (CAS latency = 3) Burst operating current (CAS latency = 2) (CAS latency = 3) Refresh current Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage HM5264405F -75 Symbol Min I CC1 I CC1 -- -- -- -- -- -- -- -- -- -- -A60 -B60 Notes 1, 2, 3 Max Min Max Min Max Unit Test conditions 60 60 1.5 1 10 5 4 3 -- -- -- -- -- -- -- -- -- -- 60 60 1.5 1 10 5 4 3 -- -- -- -- -- -- -- -- -- -- 60 60 1.5 1 10 5 4 3 18 12 mA mA mA mA mA mA mA mA mA mA CKE = VIL, tCK = 12 ns CKE = VIL, t CK = CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK = CKE = VIL, tCK = 12 ns CKE = VIL, t CK = CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK = Burst length = 1 t RC = min Standby current in power down I CC2P Standby current in power down I CC2PS (input signal stable) Standby current in non power down Standby current in non power down (input signal stable) I CC2N 6 7 4 9 1, 2, 6 2, 7 1, 2, 4 2, 9 Active standby current in power I CC3P down Active standby current in power I CC3PS down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable) I CC3N Self refresh current (L-version) I CC6 I LI I LO VOH VOL L I CC2NS I CC3NS I CC4 I CC4 I CC5 I CC6 Pr 18 12 18 12 -- -- -- -- -- -1 55 70 -- -- 55 55 -- -- 110 -- 1 0.4 1 -- -- -1 110 -- 1 -- -- -1 0.4 1 -1.5 1.5 2.4 -- -- 0.4 -1.5 1.5 2.4 -- -- 0.4 2.4 -- Data Sheet E0135H10 49 od 55 55 mA mA 110 mA 1 mA 0.4 1 mA A A V V -1.5 1.5 -- 0.4 t CK = min, BL = 4 1, 2, 5 t RC = min 3 8 VIH VCC - 0.2 V VIL 0.2 V 0 Vin VCC t uc 0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CLK operating current. 7. After power down mode, no CLK operating current. 8. After self refresh mode set, self refresh current. 9. Input signals are V IH or VIL fixed. EO Parameter Input capacitance (CLK) Input capacitance (Input) Output capacitance (DQ) Notes: 1. 2. 3. 4. 50 Capacitance (Ta = 25C, VCC, VCCQ = 3.3 V 0.3 V) Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQM, DQMU/DQML = VIH to disable Dout. This parameter is sampled and not 100% tested. L CI1 CI2 CO Symbol Min 2.5 2.5 4 Max 3.5 3.8 6.5 Unit pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 3, 4 Pr Data Sheet E0135H10 od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 AC Characteristics (Ta = 0 to +70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) HM5264165F/HM5264805F/HM5264405F EO Parameter System clock cycle time (CAS latency = 2) (CAS latency = 3) CLK high pulse width CLK low pulse width Access time from CLK (CAS latency = 2) (CAS latency = 3) Data-out hold time CLK to Data-out high impedance (CAS latency = 2, 3) Input setup time Input hold time Ref/Active to Ref/Active command period Active to Precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Transition time (rise and fall) Refresh period -75 PC/100 Symbol Symbol Min t CK t CK t CKH t CKL t AC t AC Tclk Tclk Tch Tcl Tac Tac Toh 10 7.5 2.5 2.5 -- -- 2.7 2 -- Max -- -- -- -- 6 5.4 -- -- 5.4 -A60 Min 10 10 3 3 -- -- 3 2 -- Max -- -- -- -- 6 6 -- -- 6 -B60 Min 15 10 3 3 -- -- 3 2 -- Max -- -- -- -- 8 6 -- -- 6 Unit ns ns ns ns ns ns ns ns ns 1, 2 1, 2, 3 1, 4 1 1 1, 2 Notes 1 CLK to Data-out low impedance t LZ t HZ CKE setup time for power down t CESP exit L t OH t AS , t CS, t DS, t CES t AH, t CH, t DH, t CEH t RC t RAS t RCD t RP t DPL t RRD tT t REF Pr Tsi 1.5 -- -- -- 2 2 1 Tpde Thi 1.5 0.8 Trc Tras Trcd Trp Tdpl Trrd 67.5 -- 45 20 20 10 15 1 -- 70 120000 50 20 20 10 20 1 -- -- -- -- -- 5 64 -- -- -- -- 2 2 1 -- -- -- -- ns ns ns ns 1, 5, 6 1 1, 5 1 1 1 1 1 1 Data Sheet E0135H10 51 od 70 120000 50 20 20 10 20 1 -- -- -- -- 5 64 -- 120000 ns ns ns ns ns -- -- -- -- 5 t uc ns 64 ms HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Notes: 1. 2. 3. 4. 5. 6. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is CL = 50 pF. t LZ (min) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES define CKE setup time to CLK rising edge except power down exit command. t AS /tAH: Address, tCS/tCH: CS, RAS, CAS, WE, DQM, DQMU/DQML t DS/tDH: Data-in, tCES/tCEH: CKE EO Test Conditions input 52 * Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures 2.4 V 0.4 V L 2.0 V 0.8 V t T I/O CL Pr tT Data Sheet E0135H10 od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Relationship Between Frequency and Minimum Latency HM5264165F/ HM5264805F/ HM5264405F -75 133 Symbol lRCD lRC lRAS lRP lDPL Tdpl PC/100 Symbol 7.5 3 9 6 3 2 2 1 5 9 -A60/B60 100 10 2 7 5 2 1 2 1 3 7 Notes 1 = [lRAS+ lRP] 1 1 1 1 1 2 = [lDPL + lRP] = [lRC] 3 EO Parameter Frequency (MHz) tCK (ns) Self refresh exit time (CAS latency = 3) (CAS latency = 3) DQM to data in DQM to data out CKE to CLK disable Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance (CAS latency = 2) Last data out to active command (Auto precharge, same bank) Last data out to precharge (early precharge) (CAS latency = 2) Column command to column command Write command to data in latency Register set to active command L Pr lRRD lSREX Tsrx lAPW lSEC Tdal lHZP lHZP Troh Troh lAPR lEP lEP lCCD lWCD lDID lDOD lCLE lRSA Tccd Tdwd Tdqm Tdqz Tcke Tmrd Data Sheet E0135H10 53 od 2 3 2 3 1 1 -1 -2 1 -1 -2 1 0 0 2 1 0 0 2 1 1 1 t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 HM5264165F/ HM5264805F/ HM5264405F EO Parameter Frequency (MHz) tCK (ns) CS to command disable (CAS latency = 3) (CAS latency = 3) 54 -75 133 Symbol lCDD lPEC lBSR lBSR lBSH lBSH lBSW PC/100 Symbol 7.5 0 1 1 2 2 3 0 -A60/B60 100 10 0 1 1 2 2 3 0 Notes Power down exit to command input Burst stop to output valid data hold (CAS latency = 2) Burst stop to output high impedance (CAS latency = 2) Burst stop to write data ignore Notes: 1. lRCD to l RRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP]. L Pr Data Sheet E0135H10 od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Timing Waveforms ;; ;; ;;; EO Read Cycle CLK VIH t CK t CKH t CKL t RC ;; ;; ;;;; ; ;; ;;; ;;; ;; t RCD t CS t CH t CS t CH t CS t CH t CS t CH CKE t RAS t RP CS t CS t CH t CS t CH L t CS t CH t CS t CH t AS t AH t AS t AH t AS t AH t CS Bank 0 Active Bank 0 Read t CS t CH t CS t CH RAS t CS t CH t CS t CH t CS t CH CAS t CS t CH t CS t CH t CS t CH WE Pr t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t CH t AC t AC t AC t AC t LZ t OH t OH t OH t AS t AH t AS t AH BS A10 t AS t AH Address od t HZ t OH Bank 0 Precharge DQM, DQMU/DQML DQ (input) DQ (output) CAS latency = 2 Burst length = 4 Bank 0 access = VIH or VIL t uc 55 Data Sheet E0135H10 ;; ;; ;; ;;;; HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write Cycle t CK ;;; ; ; CS t CS t CH t CS t CH t CS t CH t CS t CH EO CLK VIH t CKH t CKL t RC CKE t RCD t RAS t RP t CS t CH t CS t CH t CS t CH t CS t CH RAS t CS t CH t CS t CH t CS t CH t CS t CH L t CS t CH t AS t AH t AS t AH t AS t AH t CS Bank 0 Active CAS t CS t CH t CS t CH t CS t CH WE t AS t AH t AS t AH t AS t AH t AS t AH BS t AS t AH t AS t AH t AS t AH Pr t CH t DS t DH tDS t DH t DS t DH t DS t DH t DPL Bank 0 Write A10 t AS t AH Address DQM, DQMU/DQML od Bank 0 Precharge DQ (input) DQ (output) CAS latency = 2 Burst length = 4 Bank 0 access = VIH or VIL t uc Data Sheet E0135H10 56 ;;;; ;;; ; ;;;;;;; ;;; ;; ;; ; ;;;;;; ; ;; ;;;; ; Mode Register Set Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ;;;; ;;; ;; ; ;; HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DQM, DQMU/DQML DQ (output) DQ (input) b High-Z l RP l RSA l RCD Output mask Precharge If needed Mode Bank 3 register Active Set Bank 3 Read Read Cycle/Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CLK CS CKE VIH RAS CAS WE BS Address DQM, DQMU/DQML DQ (output) DQ (input) R:a C:a R:b C:b C:b' C:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' Bank 3 Read High-Z Bank 0 Active Bank 0 Read Bank 3 Active Bank 3 Bank 0 Read Precharge Bank 3 Read CKE CS VIH RAS CAS WE BS Address DQM, DQMU/DQML DQ (output) DQ (input) R:a C:a R:b C:b C:b' C:b" High-Z a a+1 a+2 a+3 Bank 3 Active b b+1 b+2 b+3 b' Bank 0 Precharge b'+1 b" Bank 0 Active Bank 0 Write Bank 3 Write Bank 3 Write Bank 3 Write Data Sheet E0135H10 ; b+3 b' b'+1 b'+2 b'+3 EO CLK CKE CS VIH RAS CAS WE BS Address valid code R: b C: b C: b' L l RCD = 3 CAS latency = 3 Burst length = 4 = VIH or VIL Pr 14 15 16 17 18 19 20 od b'+1 b" Bank 3 Precharge Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL b"+1 b"+2 b"+3 b"+1 b"+2 b"+3 t uc Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL Bank 3 Precharge 57 ;;; ; ;; ; ;I ;; HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read/Single Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ;;; ;; ; ; ; ; CLK CS CKE RAS CAS BS VIH EO WE Address DQM, DQMU/DQML DQ (input) R:a DQ (output) Bank 0 Active C:a R:b C:a' C:a a CKE CS RAS CAS BS WE Address DQM, DQMU/DQML DQ (input) DQ (output) L Bank 0 Read a a+1 a+2 a+3 a a+1 a+2 a+3 Bank 0 Precharge Bank 3 Active Bank 0 Bank 0 Write Read Bank 3 Precharge VIH Pr C:a R:b a a a+1 a+3 Bank 0 Read Bank 3 Active R:a C:a C:b C:c b c Bank 0 Active Bank 0 Write Bank 0 Bank 0 Write Write Bank 0 Precharge Data Sheet E0135H10 58 od Read/Single write RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = V H or VIL t uc ;; ; ; ;;; ; HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read/Burst Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ; ;; ; ; EO CLK CS CKE RAS CAS BS WE Address DQM, DQMU/DQML DQ (input) R:a DQ (output) Bank 0 Active C:a R:b C:a' a L Bank 0 Read a+1 a+2 a+3 a a+1 a+2 a+3 Clock suspend Bank 3 Active Bank 0 Write Bank 0 Precharge Bank 3 Precharge CKE CS VIH RAS CAS BS Pr C:a R:b a a a+1 a+3 Bank 0 Read Bank 3 Active WE Address DQM, DQMU/DQML DQ (input) R:a C:a a+1 a+2 a+3 DQ (output) od Bank 0 Write Bank 0 Active Bank 0 Precharge Read/Burst write RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL t uc 59 Data Sheet E0135H10 ;;; ;; ;; HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Full Page Read/Write Cycle CLK CS CKE RAS CAS VIH WE BS Address DQM, DQMU/DQML DQ (output) DQ (input) R:a C:a R:b a a+1 Bank 0 Active Bank 0 Read Bank 3 Active CKE CS VIH RAS CAS BS WE Address DQM, DQMU/DQML DQ (output) DQ (input) R:a C:a R:b a a+1 a+2 a+3 a+4 Bank 0 Active Bank 0 Write Bank 3 Active ; ; Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = full page = VIH or VIL a+2 a+3 EO 60 High-Z Burst stop Bank 3 Precharge L Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = full page = VIH or VIL Pr High-Z a+5 a+6 Burst stop Bank 3 Precharge Data Sheet E0135H10 od t uc ;;; ; ;;;; ;;; ;;; ; ; HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Auto Refresh Cycle 0 ;;;; ; ;;; ; ;;; ;; ;; ;;;;;;;; ; ;;;; ; ;; ;; ;;;; ;;; ; ; ; ;;; ;; ;; ; EO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE CS VIH RAS CAS WE BS Address DQM, DQMU/DQML A10=1 R:a C:a L t RP Precharge If needed Auto Refresh CKE Low A10=1 DQ (input) DQ (output) High-Z a a+1 t RC tRC Auto Refresh Active Bank 0 Read Bank 0 Refresh cycle and Read cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 = VIH or VIL Pr l SREX Self Refresh Cycle CLK od High-Z CKE CS RAS CAS WE BS Address t uc tRC Auto Next clock refresh enable DQM, DQMU/DQML DQ (input) DQ (output) tRP tRC Precharge command If needed Self refresh entry command Self refresh exit ignore command or No operation Next clock enable Self refresh entry command Self refresh cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL Data Sheet E0135H10 61 ;;;; ;;; ;; HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Clock Suspend Mode t CES t CEH t CES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK CS CKE RAS CAS BS WE Address DQM, DQMU/DQML DQ (output) DQ (input) R:a C:a R:b C:b a a+1 a+2 a+3 b b+1 b+2 b+3 High-Z Bank0 Active clock Active suspend start Active clock Bank0 suspend end Read Bank3 Active Read suspend start Read suspend end Bank3 Read Bank0 Precharge Earliest Bank3 Precharge CKE CS RAS CAS BS WE Address DQM, DQMU/DQML DQ (output) DQ (input) R:a C:a R:b C:b High-Z a a+1 a+2 a+3 b b+1 b+2 b+3 Bank0 Active Active clock suspend start Active clock Bank0 Bank3 supend end Write Active Write suspend start Write suspend end Bank3 Bank0 Write Precharge Earliest Bank3 Precharge ; 18 19 20 ;;;;; ; ;;;; ; ; ;;; ;; ; ;;; ;;;; EO 62 Read cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 = VIH or VIL L Write cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 = VIH or VIL Pr Data Sheet E0135H10 od t uc ;; ;; ;; ; ; ; HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Power Down Mode ;; ;; ;;; ; ;;; ;; ;; ; ;; ; 0 1 2 3 4 5 6 7 8 9 10 48 49 50 51 52 53 54 55 ;;; ; ;;; ;;; ;; ;; ;;; ; ; ;; ;; ; ;; CKE CS CKE Low EO CLK RAS CAS WE BS Address DQM, DQMU/DQML DQ (input) DQ (output) Initialization Sequence L A10=1 R: a Precharge command If needed Pr tRP Power down entry t RC Auto Refresh Auto Refresh High-Z Power down mode exit Active Bank 0 Power down cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL od High-Z CLK CKE CS VIH t uc code Valid RAS CAS WE Address valid DQM, DQMU/DQML DQ VIH t RP tRC t RSA All banks Precharge Mode register Set Bank active If needed Data Sheet E0135H10 63 HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Package Dimensions 1 0.80 0.13 M 27 *0.30 +0.10 -0.05 0.28 0.05 0.91 Max 10.16 0.13 0.05 0.10 *0.145 0.05 0.125 0.04 1.20 Max *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Mass (reference value) TTP-54D -- -- 0.53 g Data Sheet E0135H10 64 0.68 EO 54 HM5264165FTT/FLTT HM5264805FTT/FLTT HM5264405FTT/FLTT Series (TTP-54D) Unit: mm 22.22 22.72 Max 28 L Pr 11.76 0.20 0 - 5 0.80 0.50 0.10 od t uc HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Cautions 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. EO L Pr Data Sheet E0135H10 od t uc 65 |
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